Information processing device and mobile terminal

ABSTRACT

There is a need to enable decompression of a speech signal even if no network synchronizing signal is output from a baseband processing portion. For this purpose, an information processing device includes a first serial interface. The first serial interface includes a notification signal generation circuit that generates a notification signal each time compressed data incorporated from the baseband processing portion reaches a predetermined data quantity, and notifies a speech processing portion of this state using the notification signal. The speech processing portion includes a synchronizing signal generation circuit that generates a network synchronizing signal based on the notification signal. A clock signal for PCM communication is generated based on the network synchronizing signal. A speech signal can be decompressed even if no network synchronizing signal is output from the baseband processing portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2010-246282 filed onNov. 2, 2010 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to an information processing technology,an information processing device for information processing, and amobile terminal including the same.

Patent document 1 describes an information reproducing unit thatreproduces image and sound data using image and sound datacharacteristics with low power consumption. The information reproducingunit controls frequencies of a sound reproduction clock for sound datasampling based on a count clock that is controlled using timeinformation included in a received broadcast signal.

Patent document 2 describes a receiving terminal unit for receivingtransmitted digital broadcast packet data and a packet data recordingunit for recording received packet data on a tape recording medium. Thereceiving terminal unit detects a PCR identification flag from inputpackets, extracts the PCR from a packet having the PCR identificationflag, supplies the PCR to a 27-MHz phase-locked loop (PLL) circuit, andgenerates a 27-MHz synchronization signal whose time referencecorresponds to the frequency of a system clock during encoding.

Patent Document 1: Japanese Unexamined Patent Application No.2007-150809

Patent Document 2: Japanese Unexamined Patent Application No.09(1997)-186665

SUMMARY

A mobile terminal having the speech communication function includes aspeech processing portion for speech signal processing, a basebandprocessing portion for baseband signal processing, an RF (radiofrequency) portion for transmission/reception using radio frequencies,and a microcomputer for various types of information processing. Thespeech processing portion, the baseband processing portion, and themicrocomputer are provided as LSI (Large Scale Integration) circuits andare mounted on a component mounting substrate. The speech processingportion and the baseband processing portion exchange a speech signalbased on the PCM (Pulse Code Modulation) format. The speech signal issent from the speech processing portion, compressed in the basebandprocessing portion, sent to the RF portion, and then transmitted to anetwork. A signal is received in the RF portion from the network,decompressed in the baseband processing portion, and then sent to thespeech processing portion.

As mentioned above, a speech signal is exchanged between the speechprocessing portion and the baseband processing portion. In addition, amicrocomputer is provided between the speech processing portion and thebaseband processing portion and compresses and decompresses PCM signalsas described above. In this case, the baseband processing portion doesnot need to compress and decompress PCM signals. The circuit scale canbe reduced. The inventors found the following problems in the method ofusing the computer to compress and decompress PCM signals.

The baseband processing portion operates at a clock (e.g., 13 MHz)synchronized with the network. Therefore, the baseband processingportion necessarily compresses and decompresses PCM signals insynchronization with the network. However, the microcomputer operates ata clock asynchronous with the network. The baseband processing portionneeds to supply the microcomputer with a 20-ms synchronizing signal andcorrect the clock signal in the microcomputer using the synchronizingsignal when the microcomputer compresses and decompresses PCM signals.When compressing and decompressing PCM signals, the microcomputer can becombined with only a baseband processing portion that outputs thenetwork synchronizing signal to the outside.

It is an object of the invention to provide an information processingdevice capable of decompressing speech signals and a mobile terminalincluding the information processing device even if a basebandprocessing portion does not output a network synchronizing signal.

These and other objects and novel features of the invention may bereadily ascertained by referring to the following description andappended drawings.

The following summarizes representative aspects of the inventiondisclosed in this application.

The information processing device includes: a first terminal capable ofcoupling with a baseband processing portion; a second terminal capableof coupling with an audio processing portion; and a first serialinterface capable of exchanging compressed data with the basebandprocessing portion coupled through the first terminal. The informationprocessing device also includes: a speech processing portion capable ofprocessing a speech signal incorporated by the first serial interface; aclock generator that generates a clock signal for PCM communication; anda second serial interface that uses a clock signal generated from theclock generator to enable PCM communication between the audio processingportion coupled through the second terminal and the speech processingportion. The first serial interface includes a notification signalgeneration circuit that generates a notification signal each time dataincorporated from the baseband processing portion reaches apredetermined data quantity, and notifies the speech processing portionof this state using the notification signal. The speech processingportion includes a synchronizing signal generation circuit thatgenerates a network synchronizing signal based on the notificationsignal. The clock generator generates the clock signal for PCMcommunication based on the network synchronizing signal generated fromthe synchronizing signal generation circuit.

The following summarizes an effect provided by the representativeaspects of the invention disclosed in this application.

It is possible to provide an information processing device capable ofdecompressing speech signals and a mobile terminal including theinformation processing device even if a baseband processing portion doesnot output a network synchronizing signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration example of a mobileterminal having a microcomputer as an example of the informationprocessing device according to the invention;

FIG. 2 is a block diagram showing a configuration example of majorcomponents of the microcomputer shown in FIG. 1;

FIG. 3 is an operation timing chart for major components of themicrocomputer shown in FIG. 1;

FIG. 4 is another operation timing chart for major components of themicrocomputer shown in FIG. 1;

FIG. 5 is still another operation timing chart for major components ofthe microcomputer shown in FIG. 1;

FIG. 6 is yet another operation timing chart for major components of themicrocomputer shown in FIG. 1;

FIG. 7 is still yet another operation timing chart for major componentsof the microcomputer shown in FIG. 1;

FIG. 8 is a flowchart showing basic operations of the mobile terminalshown in FIG. 1;

FIG. 9 is a block diagram showing another configuration example of amobile terminal having a microcomputer as an example of the informationprocessing device according to the invention; and

FIG. 10 is a block diagram showing still another configuration exampleof a mobile terminal having a microcomputer as an example of theinformation processing device according to the invention.

DETAILED DESCRIPTION 1. Summary of the Embodiments

The following summarizes representative embodiments of the inventiondisclosed in this specification. In the following description,parenthesized reference numerals correspond to those shown in theappended drawings and just denote examples belonging to the concept ofthe corresponding components.

[1] An information processing device (1) according to a representativeembodiment of the invention includes: a first terminal (29, 30) capableof coupling with a baseband processing portion (23); a second terminal(31 to 34) capable of coupling with an audio processing portion (26); afirst serial interface (19) capable of exchanging compressed data withthe baseband processing portion coupled through the first terminal. Theinformation processing device (1) also includes: a speech processingportion (20) capable of processing a speech signal incorporated by thefirst serial interface; a clock generator (21) that generates a clocksignal for PCM communication; and a second serial interface (22) thatuses a clock signal generated from the clock generator to enable PCMcommunication between the audio processing portion coupled through thesecond terminal and the speech processing portion. The first serialinterface includes a notification signal generation circuit (195) thatgenerates a notification signal each time data incorporated from thebaseband processing portion reaches a predetermined data quantity, andnotifies the speech processing portion of this state using thenotification signal. The speech processing portion includes asynchronizing signal generation circuit (205) that generates a networksynchronizing signal based on the notification signal. The clockgenerator generates the clock signal for PCM communication based on thenetwork synchronizing signal generated from the synchronizing signalgeneration circuit.

According to the above-mentioned configuration, the notification signalgeneration circuit generates a notification signal each time compresseddata incorporated from the baseband processing portion reaches apredetermined data quantity, and notifies the speech processing portionof this state using the notification signal. The synchronizing signalgeneration circuit generates a network synchronizing signal based on thenotification signal. The information processing device can independentlygenerate a network synchronizing signal based on compressed dataincorporated from the baseband processing portion. A speech signal canbe decompressed even if no network synchronizing signal is output fromthe baseband processing portion. To compress and decompress speechsignals, the information processing device can be combined with abaseband processing portion other than that which outputs the networksynchronizing signal to the outside. That is, the system can beconfigured by combining the information processing device with even abaseband processing portion that does not output the networksynchronizing signal to the outside.

[2] According to aspect [1] above, the first serial interface mayinclude: a buffer (192) capable of outputting an incorporated signalbased on a first-in first-out method; and a pointer (1953) indicating awrite position in the buffer. The notification signal generation circuitmay include: a first threshold value register (1951) capable of settinga specified threshold value; and a first comparator (1952) that assertsthe notification signal when a write position indicated by the pointerreaches a setting value in the first threshold value register.

[3] According to aspect [2] above, the synchronizing signal generationcircuit may include: a counter (2051) that counts a specified clocksignal and is reset by the notification signal; a second threshold valueregister (2053) capable of setting an upper limit and a lower limit; anda second comparator (2052) that determines whether a count value of thecounter ranges between the upper limit and the lower limit of the secondthreshold value register. The synchronizing signal generation circuitmay also include: a pulse information register (2055) that is suppliedwith pulse information based on a determination result from the secondcomparator; and a pulse generator logic (2054) that generates thenetwork synchronizing signal at a frequency corresponding to a settingvalue for the pulse information register.

[4] According to aspect [3] above, the speech processing portion mayinclude a signal processing circuit (203) that thins out a sample orembeds silence data when a count value in the counter does not rangebetween an upper limit and a lower limit of the second threshold valueregister.

[5] According to aspect [4] above, the clock generator may include: aselector (211) that can select the network synchronizing signal outputfrom the pulse generator logic and a synchronizing signal output fromthe baseband processing portion; and a clock generation circuit (212)that generates a synchronizing signal used for speech signalcommunication.

[6] According to aspect [5] above, the first terminal may include athird terminal (30) for incorporating the synchronizing signal from thebaseband processing portion. The information processing device mayinclude a switch (90) capable of coupling the third terminal to acircuit other than the clock generator when the synchronizing signal isnot incorporated from the baseband processing portion through the thirdterminal.

[7] A mobile terminal may include: the information processing deviceaccording to aspect [5] above; a baseband processing portion coupled tothe information processing device; and an audio processing portioncoupled to the information processing device.

2. Details of the Embodiments

The following describes the embodiment in more detail.

First Embodiment

FIG. 1 shows a mobile terminal having a microcomputer as an example ofthe information processing device according to the invention.

A mobile terminal 100 shown in FIG. 1 includes a microcomputer 1, abaseband LSI (BB-LSI) 23, an RF (Radio Frequency) circuit 24, anAudio-LSI 26, a speaker 27, and a microphone 28. The microcomputer 1,the baseband LSI 23, the RF circuit 24, and the audio LSI 26 are formedover a single semiconductor substrate using, for example, single-crystalsilicon according to a known semiconductor integrated circuitmanufacturing technology.

The microcomputer 1 performs various types of information processes inaccordance with a predetermined program. The information processesinclude a process of compressing PCM signals (PCM data) sent from theaudio LSI 26 and a process of decompressing compressed data 41 sent fromthe baseband LSI 23. The decompression process for the compressed data41 is equivalent to a process of decoding the compressed data 41 andconverting it into speech data. The microcomputer 1 also providesoverall control of the information processing device. The microcomputer1 is provided with terminals 29, 30, 31, 32, 33, and 34. The terminal 29is coupled to the baseband LSI 23. The microcomputer 1 and the basebandLSI 23 exchange the compressed data 41 through the terminal 29. Theterminals 31 through 34 are coupled to the audio LSI 26. Themicrocomputer 1 and the audio LSI 26 exchange speech signals through theterminals 31 through 34. The terminal 30 is opened in this example.

The baseband LSI 23 performs a baseband process. The baseband processincludes a process of attaching a signal other than an informationsource (e.g., speech data) during transmission and a process ofseparating the information source from the other signals duringreception. Signals other than the information source include informationfor specifying communication destinations, words for timingsynchronization between transmission and reception parties, errorcontrol codes, and frame length information.

The RF circuit 24 performs transmission and reception processes based onradio frequencies through an antenna 25. The baseband LSI 23 sendsbaseband process information to the RF circuit 24. The RF circuit 24transmits the baseband process information to the network. The RFcircuit 24 receives a signal from the network and sends the signal tothe baseband processing portion 23.

The audio LSI 126 includes a function of converting a speech signalinput through the microphone 28 into a PCM code and outputting it to themicrocomputer 1 and a function of driving the speaker 27 in accordancewith the PCM code sent from the microcomputer 1.

The configuration of the microcomputer 1 will be described in detail.

The microcomputer 1 includes a central processing unit (CPU) 10, ROM(Read Only Memory) 11, a first serial interface 19, a speech processingportion 20, a clock generator 21, a second serial interface 22, anoscillator (OSC) 35, and a PLL (Phase Locked Loop) 36, for example.

The oscillator 35 generates a first clock signal CK1 at a specifiedfrequency using a crystal oscillator. The PLL 36 outputs a second clocksignal CK2 synchronized with the first clock signal CK1 output from theoscillator 35. The second clock signal CK2 is supplied as an operationclock to the components.

The central processing unit 10 is coupled to the ROM 11 through a bus12. The ROM 11 stores a program performed by the central processing unit10. The central processing unit performs the program stored in the ROM.11 to control operations for the components. The bus 12 is coupled to abus 14 via a bus bridge 16. The bus 14 is coupled to a bus 13 via a busbridge 17 and is coupled to a bus 15 via a bus bridge 18. The bus 13 iscoupled to the first serial interface 19. The buses 14 and 15 arecoupled to the speech processing portion 20.

The first serial interface 19 performs serial data communication withthe baseband LSI 23 through the terminal 29. The data communicationexchanges the compressed data 41. The first serial interface 19 includesa multiplexer/demultiplexer (MUX/DMUX) portion 191, a reception buffer(Rx FIFO) 192, a transmission buffer (Tx FIFO) 193, a bus interface (BusIF) 194, and a notification signal generation circuit 195. The receptionbuffer 192 and the transmission buffer 193 are configured as FIFObuffers. The multiplexer/demultiplexer portion 191 is coupled to thebaseband LSI 23 through the terminal 29. The bus interface 194 iscoupled to the bus 13. The compressed data 41 sent from the baseband LSI23 is sequentially stored in the reception buffer 192 via themultiplexer/demultiplexer portion 191. The compressed data stored in thereception buffer 192 is output to the bus 13 via the bus interface 194.Compressed data received from the bus 13 via the bus interface 194 issequentially stored in the transmission buffer 193. The compressed datastored in the transmission buffer 193 is output to the baseband LSI 23via the multiplexer/demultiplexer portion 191. The notification signalgeneration circuit 195 asserts a notification signal 42 each time thecompressed data stored in the reception buffer 192 reaches apredetermined data quantity. The notification signal 42 is generated tonotify this state.

The speech processing portion 20 includes RAM 201, a DMAC (Direct MemoryAccess Controller) 202, a DSP (Digital Signal Processor) 203, a pulsegenerator (PGEN) 205, a DSP control portion (DTD) 206, a pulse detectionportion 207, a buffer portion 208, and an HPB interface 209. The DSP 203compresses data (encoding) to be transmitted and decompresses thecompressed data 41 (decoding) sent from the baseband LSI 23. The RAM 201stores data compressed or decompressed by the DSP 203 included in thespeech processing portion 20. The DMAC 202 transfers data between thefirst serial interface 19 and the RAM 201 without intermediation of thecentral processing unit 10. The pulse generator 205, the DSP controlportion 206, the pulse detection portion 207, and the buffer portion 208are coupled to the DSP 203 via a bus 204. The speech processing portion20 is coupled to the audio LSI 26 via the second serial interface 22.

The buffer portion 208 includes an upload buffer (ULB), a downloadbuffer (DLB), and a selector (SEL). The selector (SEL) selectivelycouples the upload buffer (ULB) and the download buffer (DLB) to thesecond serial interface 22. The upload buffer (ULB) buffers PCM datasent from the second serial interface 22. The download buffer (DLB)buffers PCM data, that is, data decompressed in the DSP 203. Thedownload buffer (DLB) outputs the decompressed data (PCM data) to theexternally coupled audio LSI via the second serial interface 22. Theaudio LSI reproduces the PCM data and generates sound from the speaker27.

The pulse generator 205 generates a 20-ms network synchronizing signal43 based on the notification signal 42 from the notification signalgeneration circuit 195. The network synchronizing signal 43 is sent tothe clock generator 21. The notification signal generation circuit 195might assert the notification signal 42 at a timing that greatly differsfrom the reference in accordance with a change of the base stationcommunicating with the mobile terminal. In such a case, the networksynchronizing signal 43 is generated at an incorrect frequency. Thedownload buffer (DLB) might store too large or small an amount ofdecompressed data. In other words, the download buffer outputs too largeor small an amount of decompressed data (PCM data or samples) to theaudio LSI. The speaker 27 might generate unpleasant sound. To solve theproblem, a handover process is performed. The pulse generator 205determines whether the notification signal generation circuit 195asserts the notification signal 42 at a timing greatly different fromthe reference. If the notification signal 42 is asserted at a timinggreatly different from the reference, the DSP 203 retries thesynchronization and thins out decompressed data (PCM data or samples) orembeds silence data. Samples are thinned out if too many samples areavailable. Silence data is embedded if too few samples are available. Inthis manner, the handover process prevents the speaker 27 fromgenerating unpleasant sound.

The baseband LSI 23 might input a network synchronizing signal throughthe terminal 30. In this example, the handover process is also performedwhen the baseband LSI 23 inputs a network synchronizing signal throughthe terminal 30. In this case, the DSP control portion 206 controls thedecompression process in the DSP 203. The pulse detection portion 207monitors a network synchronizing signal from the baseband LSI 23 throughthe terminal 30. If the network synchronizing signal timing greatlydiffers from the reference, the DSP control portion 206 allows the DSP203 to thin out samples or embed silence data during the decompressionprocess. The handover process prevents the speaker 27 from generatingunpleasant sound.

The HPB interface 209 supplies information setting from the centralprocessing unit 10 to registers for various settings in the speechprocessing portion 20.

The clock generator 21 includes a selector 211 and a clock generationcircuit (CLK GEN) 212. The selector 211 selectively sends the networksynchronizing signal 43 from the pulse generator 205 and the networksynchronizing signal sent from the baseband LSI 23 through the terminal30 to the clock generation circuit 212. A user can determine theselection state of the selector 211 using settings of a register (notshown). If a network synchronizing signal can be incorporated from thebaseband LSI 23 through the terminal 30, the selector 211 may beconfigured to selectively send the network synchronizing signal sentthrough the terminal 30 and the network synchronizing signal 43 from thepulse generator 205 to the clock generation circuit 212. The clockgeneration circuit 212 generates a clock signal used for the PCMcommunication and a synchronizing signal SYNC for data transfer based onthe network synchronizing signal sent through the selector 211. Theclock signal used for the PCM communication contains an 8-KHzsynchronizing signal (LR) and a bit clock signal (Bit). The bit clocksignal provides sampling frequencies of 32, 64, 128, 256, and 512 fs.The synchronizing signal (Sync) and the bit clock signal (Bit) are sentto the second serial interface 22 and are sent to the audio LSI 26through the terminals 31 and 32. The synchronizing signal SYNC for datatransfer is sent to the speech processing portion 20.

The second serial interface 22 includes a transmission buffer (Tx FIFO)222, a parallel-serial conversion circuit 223, a serial-parallelconversion circuit 224, a reception buffer (Rx FIFO) 225, and an HPBinterface (HPB I/F) 226. The second serial interface 22 exchanges serialdata with the audio LSI 26 in synchronization with the 8-KHzsynchronizing signal (Sync) and the bit clock signal (Bit) generatedfrom the clock generator 21. Data is transferred between the secondserial interface 22 and the buffer portion 208 in the speech processingportion 20 in synchronization with the synchronizing signal SYNC fordata transfer. The second serial interface 22 converts data sent fromthe speech processing portion 20 into the PCM protocol and outputs it tothe audio LSI 26. The second serial interface 22 converts PCM data sentfrom the audio LSI 26 into parallel data and outputs it to the speechprocessing portion 20. The transmission buffer 222 and the receptionbuffer 225 are coupled to the buffer portion 208 in the speechprocessing portion 20 through a bus 221. The transmission buffer 222 andthe reception buffer 225 are configured as FIFO buffers. Theparallel-serial conversion circuit 223 converts parallel data sent viathe transmission buffer 222 into serial data. The serial data is sent tothe audio LSI 26 through a terminal 33. The serial-parallel conversioncircuit 224 converts serial data sent from the audio LSI 26 intoparallel data. The parallel data is sent to the speech processingportion 20 through the reception buffer 225. The HPB interface 226supplies information setting from the central processing unit 10 toregisters for various settings in the second serial interface 22.

According to the above-mentioned configuration, the compressed data 41sent from the baseband LSI 23 is incorporated into the reception buffer192 in the first serial interface 19. The speech processing portion 20is notified that the compressed data is stored in the reception buffer192. The DMAC 202 then transfers the data in the reception buffer 192 tothe RAM 201. The DSP 203 decompresses the compressed data in the RAM201. The decompressed data is sent to the second serial interface 22through the download buffer (DLB) in the buffer portion 208. The data isconverted into PCM data and is sent to the audio LSI 26 to drive thespeaker 27. Speech data input from microphone 28 is sent from the audioLSI 26 to the second serial interface 22. The data is converted intoparallel data in the second serial interface 22 and is sent to theupload buffer (ULB) in the buffer portion 208. The data in the uploadbuffer (ULB) is compressed in the DSP 203 and is stored in the RAM 201.The DMAC 202 transfers the compressed data stored in the RAM 201 to thetransmission buffer 193 in the first serial interface 19. The compresseddata transferred to the transmission buffer 193 in the first serialinterface 19 is sent to the baseband LSI 23 through the terminal 29. TheRF circuit 24 transmits the compressed data to the network.

FIG. 2 shows a configuration example of major components of themicrocomputer 1 shown in FIG. 1.

The notification signal generation circuit 195 in the first serialinterface 19 includes a register (REG) 1951, a comparator (COMP) 1952,and a pointer (POINT) 1953. The pointer 1953 indicates the current writeposition in the reception buffer 192. The position indicated by thepointer 1953 depends on the amount of data stored in the receptionbuffer 192. The register 1951 maintains a specified threshold valuesupplied from the central processing unit 10. The comparator 1952asserts the notification signal 42 to the speech processing portion 20when an output value from the pointer 1953 reaches the threshold valueplaced in the register 1951. The base station transmits packets(compressed data) at a predetermined timing. If the base stationtransmits packets at a 20-ms cycle, for example, the threshold value forthe register 1951 is specified so as to assert the notification signal42 when 52-byte compressed data is received. Accordingly, thenotification signal 42 is asserted each time 52-byte compressed data isreceived from the base station.

The pulse generator 205 in the speech processing portion 20 includes acounter (COUNT) 2051, a comparator (COMP) 2052, a register (REG) 2053, apulse generator logic (PGL) 2054, and a register (REG) 2055. The counter2051 counts a clock signal CK1 output from the oscillator 35. Thecounter 2051 is reset each time the notification signal 42 is asserted.The DSP 203 supplies two threshold values, an upper threshold value anda lower threshold value, to the register 2052. The comparator 2052 isprovided as a so-called window comparator and determines whether a countoutput value from the counter 2051 ranges between the upper and lowerthreshold values specified in the register 2052. If the count outputvalue from the counter 2051 ranges between the upper and lower thresholdvalues specified in the register 2052, the DSP 203 supplies a value tothe register 2055 based on an output value from the counter 2051immediately before the reset. The pulse generator logic 2054 asserts thenetwork synchronizing signal 43 at a cycle corresponding to the outputvalue from the register 2055. That is, a variation in the timing toassert the notification signal 42 is assumed to be allowable if thecount output value from the counter 2051 ranges between the upper andlower threshold values specified in the register 2052. The cycle of thenetwork synchronizing signal 43 reflects the variation in the timing toassert the notification signal 42. On the other hand, a variation in thetiming to assert the notification signal 42 is assumed to exceed theallowable range if the count output value from the counter 2051 does notrange between the upper and lower threshold values specified in theregister 2052. This means that the timing greatly deviates from thereference due to a change of the base station with which the mobileterminal communicates. In such a case, the DSP 203 supplies the register2055 with a standard value for generating the 20-ms networksynchronizing signal 43 in the mobile terminal 100 regardless of theoutput value from the counter 2051 immediately before the reset. Thepulse generator logic 2054 asserts the network synchronizing signal 43at a cycle corresponding to the output value from the register 2055. Thecycle of the network synchronizing signal 43 can be prevented fromvarying undesirably even if the assertion timing of the notificationsignal 42 varies outside the allowable range.

The clock generation circuit 212 in the clock generator 21 includes acounter (CONT) 2121, a comparator (COMP) 2122, a register (REG) 2123,and an LR/BT clock generation portion (LR/BT clock GEN) 2124. Thecounter 2121 counts the clock signal CK1 output from the oscillator 35.The counter 2121 is reset each time an output (network synchronizingsignal) from the selector 211 is asserted. The DSP 203 supplies twothreshold values, an upper threshold value and a lower threshold value,to the register 2123. The comparator 2122 is provided as a so-calledwindow comparator and determines whether a count output value from thecounter 2121 ranges between the upper and lower threshold valuesspecified in the register 2123. If the count output value from thecounter 2121 ranges between the upper and lower threshold valuesspecified in the register 2123, the LR/BT clock generation portion 2124generates an 8-KHz synchronizing signal (LR), a bit clock signal (Bit),and a data transfer synchronizing signal (SYNC) in synchronization withan output (network synchronizing signal) from the selector 211. If thecount output value from the counter 2121 does not range between theupper and lower threshold values specified in the register 2123, theLR/BT clock generation portion 2124 generates an 8-KHz synchronizingsignal (LR), a bit clock signal (Bit), and a data transfer synchronizingsignal (SYNC) asynchronously with an output (network synchronizingsignal) from the selector 211.

FIG. 8 shows basic operations of the mobile terminal 100 according tothe above-mentioned configuration. FIG. 3 shows operation timings forthe major components of the microcomputer 1 according to theabove-mentioned configuration.

When the mobile terminal 100 is turned on (51), the central processingunit 10 is reset to initialize the components (S2). The comparator 1952in the first serial interface 19 determines whether data is stored inthe reception buffer (Rx FIFO) 192, that is, whether an output valuefrom the pointer 1953 reaches the threshold value specified for theregister 1951 (S4). The notification signal 42 is asserted (S5) if theoutput value from the pointer 1953 reaches the threshold value specifiedfor the register 1951. The counter 2051 in the speech processing portion20 counts the clock signal CK1 output from the oscillator 35. Thecounter 2051 is reset each time the notification signal 42 is asserted.The DSP 203 supplies a value to the register 2055 based on the outputvalue from the counter 2051 immediately before the reset if the countoutput value from the counter 2051 ranges between the upper and lowerthreshold values specified for the register 2052. The pulse generatorlogic 2054 asserts the network synchronizing signal 43 at a cyclecorresponding to the output value from the register 2055. As a result,the network synchronizing signal 43 at the 20-ms cycle is generated(S6). The clock generation circuit 212 in the clock generator 21generates an 8-KHz synchronizing signal (LR), a bit clock signal (Bit),and a data transfer synchronizing signal (SYNC) in synchronization withan output (network synchronizing signal) from the selector 211 (S7). Thesecond serial interface 22 exchanges serial data with the audio LSI 26in synchronization with the 8-KHz synchronizing signal (LR) and the bitclock signal (Bit) generated from the clock generator 21. The secondserial interface 22 transfers data to the buffer portion 208 in thespeech processing portion 20 in synchronization with the data transfersynchronizing signal SYNC.

FIG. 4 shows operation timings when packets are received from thebaseband LSI 23 through the terminal 29 at an interval slightly shorterthan that shown in FIG. 3.

If packets are received from the baseband LSI 23 through the terminal 29at a slightly shorter interval, the notification signal 42 isaccordingly asserted at a shorter timing interval. The effect affectsthe cycle of the network synchronizing signal 43. The cycle of thenetwork synchronizing signal 43 also becomes shorter. The cycle of thenetwork synchronizing signal 43 is shown as 20 ms in the example ofFIGS. 3 and 19 ms in the example of FIG. 4. Changing the cycle of thenetwork synchronizing signal 43 to 19 ms generates an 8.42-KHzsynchronizing signal (LR). This causes no effect on the overalloperation.

FIG. 5 shows operation timings when packets are received from thebaseband LSI 23 through the terminal 29 at a slightly longer interval.

If packets are received from the baseband LSI 23 through the terminal 29at a slightly longer interval, the notification signal 42 is accordinglyasserted at a longer timing interval. The effect affects the cycle ofthe network synchronizing signal 43. The cycle of the networksynchronizing signal 43 also becomes longer. The cycle of the networksynchronizing signal 43 is shown as 20 ms in the example of FIGS. 3 and21 ms in the example of FIG. 5. Changing the cycle of the networksynchronizing signal 43 to 21 ms generates a 7.62-KHz synchronizingsignal (LR). This causes no effect on the overall operation.

FIG. 6 shows operation timings when packets are received from thebaseband LSI 23 through the terminal 29 at an interval greatly shorterthan that shown in FIG. 3.

A handover process is performed if packets are received from thebaseband LSI 23 through the terminal 29 at a greatly shortened intervaland a count output value from the counter 2051 does not range betweenthe upper and lower threshold values specified for the register 2052.The synchronizing signal (LR) remains 8 KHz even if packets are receivedfrom the baseband LSI 23 through the terminal 29 at a greatly shortenedinterval and the cycle of the network synchronizing signal 43temporarily changes to 10 ms, for example. In this case, too manysamples become available and are therefore thinned out during the decodeprocess of the DSP 203. Thinning out the samples prevents the speaker 27from generating unpleasant sound due to too many samples.

FIG. 7 shows operation timings when packets are received from thebaseband LSI 23 through the terminal 29 at an interval greatly longerthan that shown in FIG. 3.

A handover process is performed if packets are received from thebaseband LSI 23 through the terminal 29 at a greatly extended intervaland a count output value from the counter 2051 does not range betweenthe upper and lower threshold values specified for the register 2052.The synchronizing signal (LR) remains 8 KHz even if packets are receivedfrom the baseband LSI 23 through the terminal 29 at a greatly extendedinterval and the cycle of the network synchronizing signal 43temporarily changes to 40 ms, for example. In this case, too few samplesbecome available and silence data (null data) is embedded during thedecode process of the DSP 203. Embedding silence data (null data)prevents the speaker 27 from generating unpleasant sound due to too fewsamples.

Second Embodiment

FIG. 9 shows another configuration example of a mobile terminal having amicrocomputer as an example of the information processing deviceaccording to the invention.

The mobile terminal 100 shown in FIG. 9 mainly differs from the examplein FIG. 1 in that the mobile terminal 100 in FIG. 9 is provided with aswitch 90 capable of changing a coupling destination of the terminal 30.Settings in a register (not shown) can change the state of the switch90. The central processing unit 10 can control settings in thisregister. When the baseband LSI 23 inputs a network synchronizing signalthrough the terminal 30, the switch 90 couples the terminal 30 to theclock generator 21. When the baseband LSI 23 does not input a networksynchronizing signal through the terminal 30, the switch 90 couples theterminal 30 to an input/output portion of an internal circuit (notshown). The terminal 30 can be used as an input/output port of theinternal circuit.

Third Embodiment

FIG. 10 shows still another configuration example of a mobile terminalhaving a microcomputer as an example of the information processingdevice according to the invention.

The mobile terminal 100 shown in FIG. 10 mainly differs from the examplein FIG. 1 in that the terminal 30 in FIG. 1 is omitted. The terminal 30may be omissible if there is no need to input a network synchronizingsignal from the baseband LSI 23 through the terminal 30. The selector21, the DSP control portion 206, and the pulse detection portion 207 inFIG. 1 are also unneeded as well as the terminal 30 if there is no needto input a network synchronizing signal from the baseband LSI 23 throughthe terminal 30. It is possible to decrease the number of terminals andreduce the circuit scale.

While there have been described specific preferred embodiments of thepresent invention, it is to be distinctly understood that the presentinvention is not limited thereto but may be otherwise variously embodiedwithin the spirit and scope of the invention.

What is claimed is:
 1. An information processing device comprising: afirst terminal capable of coupling with a baseband processing portion; asecond terminal capable of coupling with an audio processing portion; afirst serial interface capable of exchanging compressed data with thebaseband processing portion coupled through the first terminal; a speechprocessing portion capable of processing a speech signal incorporated bythe first serial interface; an oscillator; a clock generator thatgenerates a clock signal for PCM communication; and a second serialinterface that uses a clock signal generated from the clock generator toenable PCM communication between the audio processing portion coupledthrough the second terminal and the speech processing portion, whereinthe first serial interface includes a notification signal generationcircuit that generates a notification signal each time compressed dataincorporated from the baseband processing portion reaches apredetermined data quantity, and notifies the speech processing portionof this state using the notification signal, wherein the speechprocessing portion includes a synchronizing signal generation circuitthat generates a network synchronizing signal based on the notificationsignal, wherein the clock generator generates the clock signal for PCMcommunication based on the network synchronizing signal generated fromthe synchronizing signal generation circuit, and wherein thesynchronizing signal generation circuit generates the networksynchronizing signal based on a clock count number which is calculatedbased on a clock signal of the oscillator from a first generation of thenotification signal to a second generation of the notification signalafter the first generation.
 2. The information processing deviceaccording to claim 1, wherein the first serial interface includes: abuffer capable of outputting an incorporated signal based on a first-infirst-out method; and a pointer indicating a write position in thebuffer, and wherein the notification signal generation circuit includes:a first threshold value register capable of setting a specifiedthreshold value; and a first comparator that asserts the notificationsignal when a write position indicated by the pointer reaches a settingvalue in the first threshold value register.
 3. The informationprocessing device according to claim 2, wherein the synchronizing signalgeneration circuit includes: a counter that counts the clock signal fromthe oscillator and is reset by the notification signal; a secondthreshold value register capable of setting an upper limit and a lowerlimit; a second comparator that determines whether a count value of thecounter ranges between the upper limit and the lower limit of the secondthreshold value register; a pulse information register that is suppliedwith pulse information based on a determination result from the secondcomparator; and a pulse generator logic that generates the networksynchronizing signal at a frequency corresponding to a setting value forthe pulse information register.
 4. The information processing deviceaccording to claim 3, wherein the speech processing portion includes asignal processing circuit that thins out a sample or embeds silence datawhen a count value in the counter does not range between an upper limitand a lower limit of the second threshold value register.
 5. Theinformation processing device according to claim 4, wherein the clockgenerator includes: a selector that can select the network synchronizingsignal output from the pulse generator logic and a synchronizing signaloutput from the baseband processing portion; and a clock generationcircuit that generates a synchronizing signal used for speech signalcommunication based on an output from the selector.
 6. The informationprocessing device according to claim 5, wherein the first terminalincludes a third terminal for incorporating the synchronizing signalfrom the baseband processing portion; and wherein the informationprocessing device includes a switch capable of coupling the thirdterminal to a circuit other than the clock generator when thesynchronizing signal is not incorporated from the baseband processingportion through the third terminal.
 7. A mobile terminal having a speechcommunication function, comprising: the information processing deviceaccording to claim 5; a baseband processing portion coupled to theinformation processing device; and an audio processing portion coupledto the information processing device.